YORKTOWN HEIGHTS, NY -- (Marketwire) -- 08/18/08 -- IBM (NYSE: IBM) and its jointdevelopment partners -- AMD, Freescale, STMicroelectronics, Toshiba and theCollege of Nanoscale Science and Engineering (CNSE) -- today announced thefirst working static random access memory (SRAM) for the 22 nanometer (nm)technology node, the world's first reported working cell built at its 300mmresearch facility in Albany, NY.SRAM chips are precursors to more complex devices such as microprocessors.
The SRAM cell utilizes a conventional six-transistor design and has an areaof 0.1um2, breaking the previous SRAM scaling barriers.
Researchers achieved this breakthrough at CNSE of the University at Albany,State University of New York. CNSE's Albany NanoTech is the world's mostadvanced university based nanoelectronics research complex. IBM and itspartners do much of their leading-edge semiconductor research at CNSE.
A nanometer is one one-billionth of a meter or about 80,000 times smallerthan the width of a human hair.
"We are working at the ultimate edge of what is possible -- progressingtoward advanced, next-generation semiconductor technologies," said Dr. T.C.Chen, vice president of Science and Technology, IBM Research. "This newdevelopment is a critical achievement in the pursuit to continually driveminiaturization in microelectronics."
22 nm is two generations away in chip manufacturing. The next generationis 32 nm -- where IBM and its partners are in development with theirleading 32 nm high-K metal gate technology that no other company orconsortium can match.
Traditionally, an SRAM chip is made more dense by shrinking its basicbuilding block, often referred to as a cell. IBM-alliance researchersoptimized the SRAM cell design and circuit layout to improve stability anddeveloped several novel fabrication processes in order to make the new SRAMcell possible. The researchers utilized high-NA immersion lithography toprint the aggressive pattern dimensions and densities and fabricated theparts in its a state-of-the-art 300mm semiconductor research environment.
SRAM cell size is a key technology metric in the semiconductor industry,and this work demonstrates IBM and its partners' continued leadership incutting-edge process technology.
Key enablers of the SRAM cell include band edge high-K metal gate stacks,transistors with less than 25 nm gate lengths, thin spacers, novelco-implants, advanced activation techniques, extremely thin silicide, anddamascene copper contacts.
Additional details of this achievement will be presented at the IEEEInternational Electron Devices (IEDM) annual technical meeting to be heldin San Francisco, CA, December 15-17, 2008.
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Michael Loughran
IBM
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